1. Field of the Invention
The present invention relates to semiconductor nonvolatile memory and, more particularly, to reduction of the applied write voltage in such memories.
2. Description of the Prior Art
For trapping electric charge permanently, a new technique has been reported which utilizes a structure wherein thin, silicon-rich, silicon dioxide layers are deposited on top of silicon dioxide film (D. J. DiMaria et al.: J. Appl. Phys., 51(9) September 1980, 4830-4841).
The above method can be used for nonvolatile semiconductor memory cells. FIG. 1 schematically illustrates in section the construction of a prior art memory cell 1 utilizing the method mentioned above.
Referring to FIG. 1, a channel region 7 is formed from an n.sup.+ drain 5 and an n.sup.+ source 9 provided within a p-type silicon substrate 3. On top of the channel region 7 there are formed a gate oxide comprised of a thin silicon dioxide film 16 (approx. 8 nm thick or more) with a silicon-rich silicon dioxide film 12 formed on top of oxide layer 16. Further on top of layer 12 and 16 there is formed an aluminum gate electrode 14.
The memory cell 1 constructed as described above has two stable information states: one in which a logic "0" has been written therein wherein electrons are trapped in silicon regions 13 within the silicon-rich silicon dioxide film 12, and the other in which the logic "0" has been erased and a logic "1" has been stored, wherein electrons are not trapped in the silicon regions 13 within the silicon-rich silicon dioxide film 12. The fact that the memory cell 1 can take the two stable information states is utilized for fabrication of a memory.
Operations of writing and erasing information into and from the aforementioned memory cell 1 are now described with reference to the hysteresis loop as shown in FIG. 2. The horizontal axis in FIG. 2 represents gate voltage V.sub.g, and the vertical axis represents threshold voltage V.sub.th. The gate voltage V.sub.g is the voltage applied to the gate electrode 14 of the memory cell relative to the source 9. The threshold voltage V.sub.th is a gate voltage at which a current begins to flow between the source 9 and the drain 5 when the voltage applied to the gate electrode relative to the source 9 is made to increase. In this case, the threshold voltage V.sub.th is given by ##EQU1## where E is silicon dielectric constant, N.sub.A is the concentration of doping impurities within the substrate, V.sub.FB is the flat band voltage, C is the capacitance of the gate insulating film, q is the quantity of electron charge, and .phi.F is the Fermi level (i.e. the potential of an intrinsic semiconductor from Fermi level).
When a logic "0" is to be written into the memory cell 1, a high voltage which may be as high as approximately 20 volts is applied to the gate electrode 14 of the memory cell 1. As a result of application of this voltage, an electric field develops between the gate electrode 14 and the channel region 7 which causes the electrons within the channel region 7 to have high potential energy. As a result, some of the electrons tunnel through the silicon dioxide film 16 and enter the silicon regions 13 within the silicon-rich, silicon dioxide film 12 and are thus trapped. Such a change in the total charge within film 12 causes the threshold voltage to increase to approximately 1.6 V (see Q1 in FIG. 2). This means that the memory cell 1 has been made to serve as an enhancement mode transistor having a threshold voltage of approximately 1.6 V. In addition, the threshold voltage will remain as it is even if the gate voltage is cut off (see R1 in FIG. 2).
On the other hand, to erase the logic "0", it is necessary to force the trapped electrons to return to the channel region 7. This is effected by generating an electric field of the opposite polarity to that produced when writing the logic "0" by applying a voltage of approximately 20 V to the channel region 7. The resulting change in trapped charge in layer 13 causes the threshold voltage to change from some 1.6 V to some -0.6 V (see S1 in FIG. 2). This means that the memory cell 1 has been made to serve as a depletion mode transistor having a threshold voltage of approximately -0.6 V. This is the stable state wherein a logic "0" is erased and the memory cell 1 has stored a logic "1". In addition, the threshold voltage will remain as it is even if the gate voltage is cut off (see T1 in FIG. 2).
Next the operation of reading information from the memory cell 1 will be described. It is decided whether a logic "0" is stored or a logic "1" is stored in each memory cell by determining whether or not current flows through the channel region 7 when a voltage of some 5 V is applied between the source 9 and the drain 5 of the memory cell 1 and no gate voltage is applied to gate 14. In other words, when a logic "1" is stored, the threshold voltage of the memory cell 1 is at a negative value, as described above. Accordingly, since the memory cell 1 then is a depletion mode transistor, and the applied gate voltage of 0 volts exceeds the threshold voltage of -0.6 volts there flows a current through the channel region 7. Meanwhile, when a logic "0" is stored, the threshold voltage of the memory cell 1 is at a positive value. Accordingly, since the memory cell 1 is then an enhancement mode transistor, the channel region 7 is non-conductive because the applied gate voltage is 0 volts and the threshold voltage is +2.6 volts. Thus no current flows through the channel region 7.
A semiconductor nonvolatile memory may be constructed by using memory cells such as described above coupled with read and write control transistor.
With progress of the semiconductor industry, the need for integrated nonvolatile semiconductor memories has arisen. Semiconductor nonvolatile memories using the conventional memory cells 1 described above have had difficulties in further integration thereof, as described below.
When a voltage is applied to the aforementioned memory cell 1 to write information therein by trapping electrons in the silicon regions 13 within the silicon-rich silicon dioxide film 12, there is a requirement that the region 11 sandwiched between the gate electrode 14 and the channel region 7 has an insulating property more than a specific level. However, since the silicon regions 13 within the silicon-rich silicon dioxide film 12 act as conductive material, the silicon-rich silicon dioxide film 12 would be insufficient as an insulator on the whole. Therefore, to enhance the insulating property of the region 11 sandwiched between the gate electrode 14 and the channel region 7, it has been required to arrange the silicon dioxide film 16 so as to be thicker than a specific level. With this thicker film, for electrons to tunnel through the silicon dioxide film 16, a high voltage as much as 20 V or so was necessary. The use of such a high write voltage requires a highly insulated structure to avoid destruction of the device caused by voltage breakdown. This has unduly restricted the degree of integration.